1. Field of the Invention
The present invention relates to an output drive circuit.
2. Description of Related Art
FIG. 4 shows an output drive circuit 1 of a semiconductor integrated circuit disclosed in Japanese Unexamined Patent Application Publication No. 2005-57573. As shown in FIG. 4, the output drive circuit 1 includes an output part 10, a bootstrap part 40, and a driving part 60. Furthermore, it also includes a drive circuit power supply terminal VDD1, an output stage power supply terminal VDD2, a ground voltage terminal GND, and an output terminal Vout. Note that, for the sake of convenience, the signs “VDD1”, “VDD2”, “GND”, and “Vout” represent the electrical potentials supplied at the respective terminals as well as the names of the terminals.
The output part 10 includes NMOS transistors QN1 and QN2. The output part 10 is a totem-pole-type output circuit using NMOS transistors QN1 and QN2 as high-side and low-side transistors respectively, and drives a load 50 by its totem-pole output.
The drain of the NMOS transistor QN1 is connected to the output stage power supply terminal VDD2, the source is connected to the output terminal Vout, and the gate is connected to a high-side drive circuit 20, which is explained later. The drain of the NMOS transistor QN2 is connected to the output terminal Vout, the source is connected to the ground voltage terminal GND, and the gate is connected to a low-side drive circuit 30, which is explained later. In the following explanation, the gate terminal of the NMOS transistor QN1 is referred to as “node B”, and the gate terminal of the NMOS transistor QN2 is referred to as “node C”.
The driving part 60 includes a high-side transistor drive circuit 20 and a low-side transistor drive circuit 30. The high-side transistor drive circuit 20 and the low-side transistor drive circuit 30 bring the NMOS transistors QN1 and QN2 to On-states or Off-states in an exclusive manner in response to the input pulse signals input to the respective drive circuits. The high-side transistor drive circuit 20 is connected to the node A. The high-side transistor drive circuit 20 drives the NMOS transistor QN1 with a voltage and a current supplied from this node A. The low-side transistor drive circuit 30 drives the NMOS transistor QN2.
The bootstrap part 40 includes a diode D1 and a capacitor C1. The anode of the diode D1 is connected to the drive circuit power supply terminal VDD1 and the cathode is connected to the node A. One terminal of the capacitor C1 is connected to the node A and the other terminal is connected to the output terminal Vout. When the NMOS transistor QN1 is to be in an On-state, the high-side transistor drive circuit 20 is driven by the bootstrap part 40.
Operations of the output drive circuit 1 are explained hereinafter. FIG. 5 shows a waveform chart for the operations of the output drive circuit 1. The operation waveforms shown in FIG. 5 represent the output voltage Vout and potential at the node B (gate potential of the NMOS transistor QN1). Note that it is assumed that the output stage power supply voltage VDD2 and the drive circuit power supply voltage VDD1 are substantially the same or very close to each other, for examples at around 10 V.
Firstly, in a period from the time 0 to the time ton_s (period toff), both the NMOS transistors QN1 and QN2 are turned off by the high-side transistor drive circuit 20 and the low-side transistor drive circuit 30 respectively. Consequently, the output terminal Vout and the ground voltage terminal GND become a short-circuit state. Therefore, the output voltage Vout is brought to the ground voltage GND. Furthermore, the potential at the node B, which is the gate potential of the NMOS transistor QN1, also falls to the ground voltage GND.
Since the potential of the output terminal Vout is the ground voltage GND, a current flows into the capacitor C1 through the diode D1, so that the capacitor C1 is charged. The charging voltage of the capacitor C1 is a potential difference between the node A and the ground voltage GND. The potential at the node A has a voltage value obtained by subtracting the forward voltage drop Vf of the diode D1 from the drive circuit power supply voltage VDD1.
Next, in a period from the time ton_s to the time ton_p (period trise), the NMOS transistor QN1 is turned on by the high-side transistor drive circuit 20, and the NMOS transistor QN2 is turned off by the low-side transistor drive circuit 30. At this point, the gate potential at the NMOS transistor QN1, i.e., a potential at the node B becomes a potential supplied from the node A through the high-side transistor drive circuit 20. Furthermore, the electrical charge charged in the capacitor C1 passes through the node A and charges the gate capacitance (not shown) of the NMOS transistor QN1 from the output of the high-side transistor drive circuit 20 (node B). As described above, the output drive circuit 1 ensures a driving voltage capable of turning on the NMOS transistor QN1, which serves as the high-side transistor, with the electrical charge charged in the capacitor C1 even when the output stage power supply voltage VDD2 and the drive circuit power supply voltage VDD1 are substantially at the same levels.
Therefore, the NMOS transistor QN1 becomes an On-state, and therefore the output voltage Vout rises. In such a case, however, the output voltage Vout becomes a voltage that is lower than a potential at the note A by an amount equivalent to the gate-on voltage VGS of the NMOS transistor QN1. Therefore, the potential at the output terminal Vout becomes a voltage value obtained by subtracting the forward voltage drop Vf of the diode D1 and the gate-on voltage VGS of the NMOS transistor QN1 from the drive circuit power supply voltage VDD1.
In a period on and after the time ton_p (period ton), the output voltage Vout and the potential at the node B are maintained at the above-described values as long as the NMOS transistor QN1, which serves as the high-side transistor, is in the On-state.
As described above, in the output drive circuit 1, the potential at the node B, which is used to turn on the NMOS transistor QN1, i.e., the gate potential of the NMOS transistor QN1 can hardly rise to the drive circuit power supply voltage VDD1 because of the voltage drop of the diode D1. Therefore, the NMOS transistor QN1 is not sufficiently driven in an On-state operation, thus impairing the starting operation to the On-state. Furthermore, when the On-state operation of the NMOS transistor QN1 is insufficient, the output voltage Vout falls from the output stage power supply voltage VDD2. Accordingly, there has been a problem that the output voltage Vout becomes unstable.